LSSD circuits have become more and more attractive for use as the size and complexity of integrated circuit chips has increased. The evolutionary increase in size, density and complexity lead to improved methods of testing and the design of circuits which are configured to enhance their testability.
Despite the existence of certain attractive aspects of LSSD circuits, they are limited to the response to input levels. That is, the level of an input signal (high or low) dictates the state that the receiving latch will go when it is clocked. The edge of a signal (transition) is not of consequence in these designs since all signals are stable when the system's synchronizing clock are activated. For this reason, interfacing LSSD circuits to devices which run asynchronously requires that the signals being received be synchronized to the receiving system clock before they are acted upon. Such synchronization always requires a wait period. This time delay penalty has an adverse impact on the system performance.
The LSSD circuits, which follow the rules generally described in U.S. Pat. Nos. 3,761,695; 3,783,254; and 3,784,907 are exemplary of efforts to enhance testability.
IBM Technical Disclosure Bulletin, Vol. 21, No. 10, March, 1979, p. 4166, "Set/Reset Shift Register Latch", D. E. Gates and W. G. Verdoorn, Jr., describes an LSSD shift register latch that is capable of being set and reset asynchronously. In this circuit, the system clock must be active to allow the latch to be either the set or reset.
IBM Technical Disclosure Bulletin, Vol. 23, No. 5, October, 1980, p. 2013, "Edge Triggered Latch Design", R. A. Johnson, describes an edge triggered Latch which is limited to synchronous operation.
IBM Technical Disclosure Bulletin, Vol. 24, No. 1A, June, 1981, p. 404, "Signal Transition Detection Circuit", J. W. Cannon and B. D. Herrman, describes an edge triggered latch which is intended for synchronous operation.
IBM Technical Disclosure Bulletin, Vol. 24, No. 2, July, 1981, p. 1038, "Level Sensitive Scan Design Testable Asynchronous Set/Reset Latch", is descriptive of a synchronous latch in which the scan clock is used to reset the latch.
U.S. Pat. No. 4,277,699, Brown et al., shows a "D" type flip flop which utilizes a synchronous clock signal.
IBM Technical Disclosure Bulletin, Vol. 27, No. 12, May, 1985, p. 7120, "LSSD Design Techniques", discloses techniques for meeting the rules of LSSD in an edge triggered shift register latch. The latch is designed for synchronous operation.
U.S. Pat. No. 4,580,137, T. S. Fielder and R. P. Moore, shows a latch circuit which provides synchronous and asynchronous clocking. This patent contains an exceptionally complete review of the various aspects of LSSD latch design.
U.S. Pat. No. 4,692,633, C. H. Ngai and G. J. Watkins, shows a latch design for synchronous operation.